Yashomathi Batkeeri

About Yashomathi Batkeeri

I’m a Master’s student in Computer Engineering at Arizona State University (graduating Dec 2025) with a strong focus on VLSI design, digital design, and computer architecture. My experience spans the full RTL-to-GDSII design flow, including low-power methodologies, static timing analysis (STA), and performance optimization for modern computing systems.I’ve built and optimized systems across RTL, microarchitecture, and physical design, with hands-on work in arithmetic units (ALU, FPU, multipliers), cache policies, branch predictors, and custom accelerators. On the physical design side, I’ve implemented ASIC flows in 7nm (synthesis, P&R, STA, power analysis) and designed custom SRAM arrays with verification across PVT corners.I’m also experienced in machine learning acceleration, having designed FPGA-based CNN accelerators and custom function units for model optimization.Tools: Cadence Innovus, Synopsys Design Compiler & PrimeTime, ModelSim, VCS, Vivado, GEM5, and open-source EDA toolchains.I’m currently seeking Fall 2025 co-op and full-time opportunities in hardware design, computer architecture, and high-performance/low-power computing, where I can contribute to building efficient, scalable, and high-performance systems.

Experience

1. Intern, Power Analysis

   Tenstorrent

   Dec 2025 — Present · Santa Clara, CA, US

Education

• University College of Engineering, Osmania University

  Bachelor of Engineering - BE, Electronics and Communications Engineering

  2019 — 2023

• Arizona State University

  Master's degree, Computer Engineering (Electrical)