Yashika Gupta

About Yashika Gupta

Currently I work with power optimization RnD, majorly creating and verifying power reduction techniques and flows at RTL scale. I have a good experience of unit testing and regression analysis. I have a great experience of benchmark design analysis and customer design debugging with in depth knowledge of bash scripts and Tcl.Completed B.TECH In Electronics & Communication Engineering 2021 Batch pass-outKey skills. HDL : Verilog. HVL : System Verilog. Scripting language: PERL, C-shell, TCL. Communication protocol : UART, I2C, SPI. Programming language : C & Data structure. Strong fundamentals of Digital electronics. Miscellonous : Static time analysis, CMOS concept.Tools : Questa-Sim, Xillinx- ISE, Proteus, EDA Playground. Platform : Windows,Linux Have a good knowledge about RTL Synthesis concepts & Testbences in verilog & System VerilogProficient in writing System Verilog Testbench Environment

Experience

1. Lead Product Engineer

   Cadence

   Nov 2025 — Present

Education

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech

• YMCA University of Science & Technology

  Bachelor's degree, , Electronics and Communications Engineelring

  2017 — 2021