Yashaswini Dj
DFT @ Intel
- Role
- Dft Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Yashaswini Dj
6 years of VLSI industrial experienceExperience Responsible for DFT pattern generation, simulations and debug (including setup enablement, required automations). Experience in constraints development for DRC cleaning. Experience in coverage analysis/improvement for various models like stuckat and transition faults. Handled gate level pattern simulations (Zero delay & Timing). Tools : Mentor Testkompress, Synopsys Verdi, Spyglass DFT, Spyglass Lint & VCS. Scripting : Shell, Perl Language: verilog,VHDL. Version Control - git
Experience
Dft Engineer
Jan 2025 — Present
Education
REVA University
Master of Technology - MTech, VLSI
Skills
- Fpga Design
- C
- Vhdl
- Static Timing Analysis
- Microcontroller
- C++
- Comsol
- Verilog
- Modelsim
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