Yashasvi Ponnam

About Yashasvi Ponnam

Have a thorough knowledge on all the stages of Place and Route flow from Netlist to GDSII [Including STA/DRC/LVS/].• Was part of multiple tapeouts in SF2, 4FF, 5LPE, 7FF, 16FFP, GF 14nm LPP tech nodes.• Have good knowledge and worked on the blocks that uses Low Power design Techniques - Clustering, Power Gating, Multi-Voltage design [UPF Flow].• Currently Part of Qualcomm CPU team, working on leading the implementation of the CPUSSWorked on construction and timing closure of blocks that include DDR PHY and its interface controller logic.• Have knowledge on SSB Timing and construction.• Worked on Full Chip Clocks timing closure in the last three projects.• Responsible for closing a timing critical block in a project by building custom clock tree and performing other clock tree experiments.• Well versed in using, Cadence Innovus, Synopsys Fusion Compiler, IC Compiler-II and Primetime.Good at TCL, Perl & Shell scripting

Experience

1. Staff Engineer (Cpu Pd)

   Qualcomm

   Dec 2023 — Present · Hyderabad, IN

Education

• Vignan Institute of Technology & Science, JNTU Hyderabad

  B.Tech, Electronics & Communication Engineering

  2007 — 2011

• Microsoft Research Summer School, IISC

  Wireless Networking

  2014 — 2014

• Chaitanya Bharati Institute of Technology(CBIT) , Osmania University

  Master of Engineering (M.E), Electrical, Electronics and Communications Engineering

  2011 — 2013

Skills

• Python
• Unix
• Gps Navigation
• Microcontrollers
• Tcl
• Synopsys Formality
• Modelsim
• Cadence Encounter
• Communication
• C
• Ic
• Redhawk
• Networking
• Static Timing Analysis
• Synopsys Tools
• Digital Circuit Design
• Matlab
• Pspice
• Digital Signal Processing
• C Shell Programming
• Synopsys Primetime
• Perl
• Embedded Systems
• Wireless
• Gps