Yash Pakhale
Microsoft | AMD | MS-EE(Honors) at USC
- Role
- Silicon Design Engineer at Microsoft
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
About Yash Pakhale
I am passionate about exploring latest advancements in technological field. I am…
Experience
Silicon Design Engineer
Jun 2025 — Present · Mountain View, CA, US
Conducted performance and power modeling for compute subsystems- Responsible for Fmax (maximum frequency) calculations and Voltage-Frequency (VF) curve characterization to support silicon performance scaling and efficiency analysis- Performed die grading tasks, analyzing silicon samples to classify bins based on electrical and thermal behavior.
Education
Rayat Shikshan Sanstha
SSC
2008 — 2015
Arihant Education Foundations Arts,Science & Commerce College, Pune
Science
2015 — 2017
MIT World Peace University
Bachelor of Technology - BTech
2017 — 2021
University of Southern California
Master of Science - MS
2023 — 2025
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.