Yash Chaturani
Design Engineer 1 at Cadence Design Systems
- Role
- Design Engineer 1 at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Yash Chaturani
Primary interests: reconfigurable computing and low-power VLSI design Also…
Experience
Design Engineer 1
Jun 2024 — Present · Bengaluru, IN
Working as a Post Silicon validation engineer performing PHY layer electrical validation of High Speed SerDes IPs targeted towards the Ethernet protocol achieving data rates up to 212 Gbps.Worked on a variety of specifications - 802.3, OIF-CEI and JESD204, and with many standard lab instruments like oscilloscopes, spectrum analyzer and Bit error rate tester.
Education
Timpany Senior Secondary School
ICSE, 10th grade
National Institute of Technology, Tiruchirappalli
Bachelor of Technology - BTech, Electrical and Electronics Engineering
2020 — 2024
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