Sai Pavan Yaraguti
- Role
- Staff Verification Engineer at Arteris
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Sai Pavan Yaraguti
Working as a verification engineer since August 2013
Experience
Staff Verification Engineer
Mar 2022 — Present
Skills
- Perl
- Integrated Circuit Design
- Rtl Verification
- Functional Verification
- Xilinx
- Python
- Semiconductors
- Matlab
- Rtl Coding
- Linux
- Systemverilog
- Asic
- Verilog
- I2c
- Semiconductor Industry
- Amba Apb Protocol
- Mixed Signal Verification
- Very-Large-Scale Integration (Vlsi)
- C
- Modelsim
- Vlsi
- Electrical Engineering
- Computer Architecture
- Perl Script
- Java
- Html 5
- Eclipse
- Uvm
- Vhdl
- Verdi
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.