Phil

Gpu Hardware Intern @Imagination Technologies

GB

Spearheaded the restoration of over 15 SystemVerilog testbenches for a down-scaled GPU product, resolving compilation failures from VHDL-to-SystemVerilog conversion and down-scaling- Automated syntax and package updates using Python and Unix sed, improving testbench scalability and reducing manual verification time- Diagnosed and resolved UVM scoreboard mismatches in sanity tests by analysing VPD waveforms, RTL design and transaction interfaces, enhancing test reliability across multiple configurations- Improved frame buffer header data correctness from 97.7% to 100.0%, enabling successful rendering of sample images- Verified compilation and sanity tests for PDS (Programme Data Sequencer) and FBCDC (Frame Buffer Compressor/Decompressor) modules, collaborating with RTL designers to trace data propagation issues and refine reference models for regression stability.

University of Cambridge

Master of Engineering - MEng

KTJ Primary Secondary Academia Kolej Tuanku Ja'afar

Cambridge IGCSE and Cambridge A-levels