Yankun Li
Design Engineering Director at Cadence Design Systems
- Role
- Design Engineering Director at Cadence
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Yankun Li
Specialized in RTL design and verification with Verilog/SystemVerilog language. Proficient with verification methodology such as VMM and UVM.Now leading on GDDR6/7, LPDDR5x PHY FE development Knowledge of telecommunication networking,switch,router,baseband,DDR controller and PHY.
Experience
Design Engineering Director
Jul 2022 — Present · San Jose, CA, US
GDDR PHY IP Frontend Owner. Technical Lead and Frontend owner of GDDR6/7 PHY IP. Silicon approved 16 and 24Gbps G6 PHY IP already provided to multiple automotive and AI customers across process nodes.Lead team developed the GDDR7 PAM3 PHY.Now GDDR7 36Gbps silicon approved.
Education
Xidian University
Master's degree, Microelectronics
2007 — 2010
Xidian University
Bachelor's degree, Electronics science and technology
2003 — 2007
Skills
- Network Switch/Router
- Microprocessors
- Uvm
- Adsl
- Rtl Design
- Baseband
- Soc
- Vmm
- Asic
- Functional Verification
- Systemverilog
- Amba Ahb
- Open Verification Methodology
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