Yang Hong

Staff Engineer @Intel

2018~present:@ N7/N5P/N3E\\\\n3rd party SRAM compilers comparison/interface to 3rd party memory IP vendors\\\\nPPA optimization for multiple projects targeting modem and other high-performance low-power SoCs\\\\nIn-house PPA optimizer testing, debug & improvement with in-house library generation flow based on 3rd party memory compilers.\\\\n\\\\n2017~present :@ 28HPC+/16FFC\\\\nDesign enablement lead in c16ffc (next-gen Smartphone-based RF chips, WIFI/BT, auto radar.) and memory interface to Si foundry.\\\\nECC/repair signoff for on-die memories with yield prediction\\\\nWAC (Wafer Acceptance Criteria) signoff for on-die memories, SRAM centering with leakage calibration\\\\n3rd party SRAM compilers comparison and PPA optimization for RF projects by using some of 3rd party SRAM compilers.\\\\nlibrary generation flow development and optimization for 3rd party SRAM compiler\\\\nc16 silicon bring-up/ramp support lead on memory topics, e.g. PCM/WAC/SRAM Vmin yield/HTOL/DVS/HVQK/in-field DPM/FA.\\\\nmemory interface to both Si Foundry and 3rd Party IP vendors\\\\n\\\\n20••••17: 10/14nm in-house LP memory cell technology & memory architecture optimization for slim modem / SoC / other products (e.g. XMM7560/7660, Cannonlake-PCH/Icelake-PCH)\\\\nT0 Vmin signoff with DPM optimization for different use cases (consumer/automotive)\\\\nPower KPI analysis with yield loss and DPM optimization\\\\nDynamic power/leakage reduction with novel structure or novel NVM/SRAM architecture.\\\\n\\\\nseveral patents granted or application filed for embedded SRAM/RF/NVM IPs.\\\\n \\\\n\\\\n \\\\n \\\\n\\\\n \\\\n