Yamini Thottadi

About Yamini Thottadi

Skilled in UVM based testbench development, VIPs, System Verilog, OOPs concept, Verilog, FPGA/ASIC product cycle at SOC, System and Sub-system level. Experience in standard bus protocol verification such as AXI,AHB,I2C,I3C and working knowledge of PCIE. Experience in integrating industry-based VIPs in the testbench environment and configuration.

Experience

1. Senior Verification Engineer

   L&T Technology Services

   Jul 2024 — Present · Hyderabad, IN

   Verified ARM CoreSight debug & trace components integrated with Cortex-R52, focusing on trace accuracy and debug signal correctness.•Enhanced UVM testbench components including monitors, scoreboards, and reusable sequences for trace-path validation.•Supported integration-level debug across trace paths and Cross Trigger Interfaces (CTI) to ensure correct interaction with CPU/system IPs.•Triaged regression failures, isolated root causes, and collaborated with design teams for fix verification and closure.Worked on RAL model enablement/validation and interrupt-related verification scenarios for the Soundwave ARM IP subsystem.•Executed and extended UVM register sequences to validate register accessibility, reset behavior, and field-level functionality.•Refined bus adapter mapping for frontdoor/backdoor access paths and improved register test stability.•Developed interrupt testcases (C/ASM as applicable) to validate multiple interrupt generation/handling conditions.•Supported regression runs and waveform-based debug; improved stability of test sequences and checks.

Education

• Miracle Educational Society Group of Institutions, Miracle City, Bhogapuram Mandal PIN-535216

  Electronics and communications , Bachelor Of Technology

  2011 — 2015

• Vignana Jyothi Residential School

  SSC

  2008 — 2009

• Vignana Jyothi Institute - India

  Intermediate

  2009 — 2011