Yajur Pandit

About Yajur Pandit

12 Years Experience in bug hunting Able to motivate/lead/guide and drive multiple team members to achieve project goals and milestone.• Test Bench Architecture And Environment Development • Feature Extraction from RFC and Design Doc• Feature Plan, Test Plan, Checker Plan, Coverage Plan And Feature To Test Mapping • Firmware Development, Error Handling And Error Injection • Assertion And Cover Property Coding• Sanity And Regression Clean-Up• Function/Code Coverage Development And Closer• Architecture, Code Reviews• Basic Knowledge Of Automatic Formal Analysis Using Incisive Formal Verifier (IFV).• Implemented C++ Reference ModelHave Ramp up multiple team membersHave trained multiple interns from institutes like NITs for Oops, Systemverilog and UVM.Protocol : RoCE, IBT, RoCEv2, TCP, NVMeOf Over TCP, Ethernet, AMBA AXI4, AMBA AXI Steaming System Verilog, C, C++, UVM. Code coverage and Functional coverage analysis TLM1 & TLM2 Onsite experience : Hyderabad, India, Suwon, South Korea, California USA Hands on debuggingTools : VCS, QuestaSim and Cadence.Languages : System Verilog, Verilog, C, C++.Methodology : UVM.

Experience

1. Asic Verification Engineer

   Meta

   Jun 2024 — Present · Bengaluru, IN

Education

• Symbiosis Centre for Distance Learning

  Post Graduate Diploma in Business Administration with Operation Specialization, Operation Management with Technology and project management specialization

  2013 — 2015

• Gujarat Technological University

  Bachelor's degree from Om Shanti Engineering College,Rajkot , Electrical, Electronics and Communications Engineering

  2009 — 2012

• Earthinators Climate School

  Diploma in, Electronics and Communication

  2006 — 2009

Skills

• C++
• Uvm
• Microprocessors
• System Verilog
• Universal Verification Methodology (Uvm)
• Very-Large-Scale Integration (Vlsi)
• Verilog
• Vcs
• Incisive Formal Verifier
• C
• Programming
• Objective-C
• Perl
• Embedded Systems
• Eda
• Application-Specific Integrated Circuits (Asic)
• Linux
• Perl Script
• Embedded C
• Rtl Verification
• Systemverilog
• Questa
• Vlsi
• Asic
• Functional Verification