y Patil
Senior Analog Design Engineer @SmartSoC Solutions Pvt Ltd
Hyderabad, TG, IN
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Apr 2024 — Present
Senior Analog Design Engineer @SmartSoC Solutions Pvt Ltd
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IN
worked on DRC2 & XSEL testcases. and standard cells
EDUCATION
N/A
Visvesvaraya Technological University
Bachelor of Engineering - BE, Electronics and communication
ABOUT Y PATIL
senior analog Layout designer
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