Mahesh Chandra Yachamaneni

About Mahesh Chandra Yachamaneni

As an EDA Tools Software Engineer at Intel, I work on Process Design Kits (PDKs) for cutting-edge nodes. My primary responsibilities include developing and validating APR collaterals (tech file, map files, and codesign files) for PDKs, validating the tech file\'s design rule modeling at unit-level, and running RTL2GDSII flow on block-level testcases to analyze physical convergence (DRC, LVS, etc.) Furthermore, I support the development of ASIC APR reference flows, work on EDA tool capability enablement projects, and collaborate with EDA vendors to resolve tool issues.I earned my Masters degree in Computer Engineering from Arizona State University in 2022, scoring a CGPA of 3.7. My coursework focused on digital circuits and VLSI design, including several custom and ASIC design projects using 32nm and 7nm nodes. I worked as a Product Development Engineer Intern at Intel during my last semester, focusing on Scan ATPG and Python scripting.Before graduate study, I worked as a Software Engineer for 3 years at HCL Technologies. During my tenure, I ideated and implemented 3 test automation solutions to alleviate customer pain-points and improve process efficiency, saving $95k per year.Some of my achievements include:• Achiever’s League – O’ Infinity Award: For delivering an outstanding performance and demonstrating leadership skills during a critical project.• Rewards and Recognition QA: For acquiring domain knowledge in a short span and helping the team build a cross-browser automated testing solution for 1400 test cases.

Experience

1. Eda Tools Software Engineer

   Intel

   Jul 2024 — Present · Chandler, AZ, US

   Developing ASIC APR technology collaterals (technology file, VMF, and map files) for sub-angstrom node PDKs.• Running unit-level metal and via DRC checks to ensure alignment between physical verification runset and tech file.• Maintaining Ruby-based automation infrastructure of custom CAD tools used for collateral generation.• Enabling reference RTL2GDS flows (for adoption by internal and external design teams) by integrating vendor-provided base physical design scripts with technology node-specific scripts.• Creating and updating User Guide and Release Notes documentation for reference flow releases.• Executing APR and signoff flows on complex design blocks across various libraries and track patterns using Fusion Compiler and IC Validator.• Analyzing physical convergence (DRC, LVS, antenna, physical integration) reports and fixing any tool or PDK issues by collaborating with vendors and internal teams.• Collaborating with EDA vendors to drive APR enhancements and bug fixes in Fusion Compiler.• Driving EDA tool (Fusion Compiler) certification efforts by working with Foundry and vendor (Synopsys) to certify latest PDKs on QoR, convergence, special APR features, RC and timing correlation.

Education

• Arizona State University

  Master of Science - MS, Computer Engineering (Electrical Engineering)

• Sri Gayatri Junior College

  Intermediate, MPC

  2013 — 2015

• P.B.D.A.V Model School

  SSC

• Sathyabama Institute of Science & Technology, Chennai

  Bachelor of Engineering - BE, Electronics and Communication Engineering