Xiongfei Meng

About Xiongfei Meng

At Nvidia- GPU and AI data center chips: silicon debug and learnings to improve…

Experience

1. Principal Engineer

   NVIDIA

   Mar 2020 — Present

   Deep dive into silicon learnings (e.g, variation/limitations/boundaries) from GPU and AI data center chips (largest chips from latest tech nodes) Silicon debug and correlation to design: fed back what we learned from silicon into design methodology Advanced tech node enablement through PPA trials P&R and timing recipes/methodologies for PPA improvement Parametric-limited yield improvement, silicon Fmax/Vmin improvement, process enhancement Test chip planning and silicon learnings for P&R, PPA

Education

• The University of British Columbia

  B.A.Sc. (with Distinction), Electrical Engineering

  2001 — 2004

• The University of British Columbia

  PhD, Electrical Engineering

  2006 — 2009

• The University of British Columbia

  M.A.Sc., Electrical Engineering

  2004 — 2006

Skills

• Application-Specific Integrated Circuits (Asic)
• Primetime
• Analog
• Field-Programmable Gate Arrays (Fpga)
• Eda
• Systemverilog
• Cadence Virtuoso
• Vlsi
• Very-Large-Scale Integration (Vlsi)
• Timing Closure
• Static Timing Analysis
• Soc
• Physical Design
• Analog Circuit Design
• Electronics
• Asic
• Cmos
• Integrated Circuit Design
• Verilog
• Semiconductors
• Ic
• Testing
• Fpga
• Low-Power Design
• Tcl
• Place & Route
• Rtl Design
• Clock Tree Synthesis
• Mixed Signal
• Vhdl
• Computer Architecture
• Dft