Xiaozhou Hu
Physical Design Verification Engineer
- Role
- Physical Design Verification Engineer (Pd Engr) at Samsung Semiconductor
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
Experience
Physical Design Verification Engineer (Pd Engr)
Mar 2022 — Present · San Jose, CA, US
Accomplishments Working on 14nm/10nm design Working as physical design verification engineer (including LVS/DRC/ERC/ANT, debugging fixes) using ICC2/Calibre Fixing LVS/DRC/ERC/ANT violations Working on place-n-route works for 14nm and 8nm.
Skills
- Soc
- Semiconductors
- Verilog
- Icc
- Virtuoso
- Ic
- Asic
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