Xiaoye Jing

About Xiaoye Jing

Hands-on design experience in RF PLL, high performance data converter and other…

Experience

1. Senior Member of Technical Staff

   AMD

   Jan 2016 — Present

   Involved in clocking architecture definition for graphics ddr phy and AMD’s custom serdes phy (tsmc n7 and gf14) • RF pll loop modeling for phase noise/jitter analysis and block level spec derivation pll-I: low bandwidth, lc vco based pll for noise filtering and low-jitter clock pll-II: high bandwidth, dual loop, ring vco based pll for multi-phase clock • Designed from scratch of lc vco (13GHz – 16GHz) and entire high speed cml clock path • Performed all electrical checks (spice-check, fanout check, EMIR, Sigem, Aging etc) for design signoff • Point of contact for pll silicon bring up and guided pll characterizations • A0 silicon success