Xavier P J
Lead Design Engineer at Cadence Design Systems
- Role
- Lead Design Engineer at 铿腾设计系统公司
- Location
- Thrissur, KL, IN
- LinkedIn followers
- 500 followers
About Xavier P J
8+ years experience in analog layout.* worked on diferent high speed transmitter architectures*worked on multiple analog blocks-TX/RX/PLL/BANDGAP/ILL/LDO/PI/CLOCK TREE/SERIALIZER/DE-SERIALIZER*worked on DDR4/5,GDDR6/7,LPDDR4/5,UCIE AP,USB2*worked on tsmc 28/16/12/7/6/5/4/3/2 Samsung10/8/7/5/4/3/2 GF 14 foundary nodes*worked in planar fet/Finfet/GAA Fet
Experience
Lead Design Engineer
Jun 2024 — Present · Bengaluru, IN
Lead Design Engineer
Education
Maharaja's Technological Institute
Diploma of Education, Electrical and Electronics Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.