Wei Han
Sr. Manager SoC Design Engineering
- Role
- Senior Manager Soc Logic Design Engineering at Intel
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Wei Han
Wei Han is a hands-on SOC and ASIC development leader with a history of numerous high volume, high profile IC products with 1st-pass success in the fields of networking, AI Connectivity, communication and power management. Highly skilled in team building, mentorship, project management, risk management, and design methodology. Extensive experience and success in digital RTL and mixed-signal IC architecture and design and implementation of embedded micro-controllers such ARM, Xtensa, and DSP processors.
Experience
Senior Manager Soc Logic Design Engineering
Aug 2022 — Present · Austin, TX, US
Lead a high performance team of micro-architects, RTL design engineers, and design verification engineers on design of RDMA and other advanced IPs based on PCIe, InfiniBand, TCP/IP, or RoCE protocols in Cloud, Networking, and AI Connectivity applications.• Manage projects to meet aggressive project schedule and work with internal and external customers on milestones, IP delivery flow, new features evaluation and trade off discussions.• Strong focus on robust planning and effective execution. Implemented and lead a phased development and release strategy with a focus on task ownership, schedule commitment, and quality delivery.• Hands-on ownership of design tasks for major functionality involving multiple high-performance embedded microprocessors and FW/HW architecture development.
Education
Beijing Jiaotong University
BS, Electridal Engineering
University of Minnesota
MS, Electrical Engineering
Skills
- Ic
- Fpga
- Asic
- Eda
- Semiconductors
- Rtl Design
- Verilog
- Digital Signal Processors
- Analog Circuit Design
- Cmos
- Analog
- Vlsi
- Soc
- Mixed Signal
- Circuit Design
- Static Timing Analysis
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