Wayne Yun

Fellow, Pmts, Smts, Mts @AMD

An architect in DV driving formal verification, UVM and best practices * Formal verification using Synopsys VC Formal and SystemVerilog Assertion (SVA)- End-to-end sign-off of micro-controller, equalization/adaptation logic of high speed serial link, AHB arbiter, CSR registers - Formally checked legality of firmware instructions and their combinations - Successfully deployed APPs of FPV, SEC/SEQ, COV, CC, FTA * UVM/OVM testbench architecture - Innovated testbench architecture for project requirements - parameterized interface, stitching UVM/C/C++ TBs into higher level, RAL model at integration level - Architected PCI Express testbench, consulted multiple other TBs - Connected to emulator and virtual prototype - Promoted mutation coverage * Verified Ethernet PCS and controller - Created UVM TB connecting Verilog VIP - 10GBASE-KR, XGMII, GMII, SGMII, AXI, UNH * Architect and lead of PCIe VIP/BFM - C/C++, SystemC, SystemVerilog, DPI, UVM, STL