Vineeth Vs
Design Verification Engineer at Broadcom Limited
- Role
- Staff Engineer at Broadcom
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vineeth Vs
IP/Block level verification, SoC verificationProtocols: SPI, AMBA APB, AHB, AXI, MIPI-MPHYLanguages: SystemVerilog, VerilogMethodology: UVM, OVMSimulators: VCS, Questasim, ModelSim, NCsim.
Experience
Staff Engineer
Sep 2014 — Present
ASIC verification SAS/SATA controller/expander SoC using SV-UVM. Testbench development Functional coverage, code coverage, checkers and assertions Gate level simulations.
Education
University of Calicut
B.Tech, Electronics & Communication
2006 — 2010
Sandeepani School of VLSI Design and Verification
PDC, VLSI design and Verification
2011 — 2011
H.S.Kadampazhipuram
Primary School
1997 — 1998
Sainik School Kazhakootam (SSKZM)
High School
1998 — 2005
G.U.P.S Kadampazhipuram
Primary Schooling
1993 — 1997
Skills
- Rtl Coding
- Universal Verification Methodology(Uvm)
- Vlsi
- Xilinx
- Systemverilog
- Ncsim
- Open Verification Methodology
- Uvm
- Fpga
- Asic
- Digital Design
- Verilog
- Integrated Circuit Design
- Rtl Design
- Vmm
- Soc
- Universal Verification Methodology (Uvm)
- Modelsim
- Functional Verification
- Application-Specific Integrated Circuits (Asic)
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