Vishal Prajapati
ASIC Design Engineer
- Role
- Design Engineer at Marvell Technology
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Vishal Prajapati
Success in leveraging deep understanding of ASIC IP design flow, encompassing micro-architecture, RTL design, IP integration and simulation debug. Specializing in PCIe Speed Adapter solutions on the ZeBu server emulation platform, with a strong record enabling customer deployments and hands-on system debug experience. Proficient in leveraging cutting-edge design/emulation tools and technologies to enhance product functionality. Proficient in quickly learning new technologies and applying them to develop innovative solutions.
Experience
Design Engineer
Feb 2026 — Present · Santa Clara, CA, US
Education
San José State University
Master of Science (M.S.), Electrical and Electronics Engineering
2013 — 2015
The Maharaja Sayajirao University of Baroda
Bachelor of Engineering (BE), Electronics Engineering
2008 — 2012
Skills
- Application-Specific Integrated Circuits (Asic)
- Rtl Design
- Keil
- Matlab
- Vhdl
- Powerpoint
- Microsoft Excel
- Html
- Microsoft Word
- Atmel Avr
- Microprocessors
- Debugging
- Verilog
- Pspice
- Windows
- Microcontrollers
- Modelsim
- Ni Multisim
- Systemverilog
- C
- Microsoft Office
- Asic
- Multisim
- Outlook
- Perl
- Embedded Systems
- Xilinx Ise
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.