Dilip Daneti
Senior CPU Performance Monitoring Engineer
- Role
- Senior Cpu Performance Monitoring Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Dilip Daneti
Performance Monitoring Engineer working on Validation of monitoring events and metrics used in Performance Analysis tools for Intel Server Xeon and Client Hybrid Platforms.Interests: Computer Architecture, Performance Analysis.
Experience
Senior Cpu Performance Monitoring Engineer
Jun 2019 — Present · US
Pre silicon validation of performance monitoring events. Verifying the correlation of the CPU performance models to the RTL implementation using cycle-accurate/approximate performance models and analysis.• Lead Post-silicon validation of P Core performance monitoring events.• Developing methodologies for using events to characterize system performance.• Develop tests, test plans, and testing infrastructure for new architectures/features.• Working with architects to understand and explain events and their programming in tools, articles, and documentation.• Providing training to internal or external monitoring users.• Debugging HW monitoring issues in Intel analysis tools.• Influencing the direction of future HW monitoring technologies on our platforms.• Developing software infrastructure, tests, tools, and prototypes needed to support the above tasks.
Education
Portland State University
Master of Science (M.S.), Electrical and Computer Engineering
Jawaharlal Nehru Technological University
Bachelor’s Degree, Electrical and Electronics Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.