Vikas Rao

About Vikas Rao

I specialize in formal hardware verification, datapath circuit rectification, and FPGA-based prototyping, with a strong foundation in algorithms, solvers, and graph-based verification techniques. My work bridges advanced research and practical implementation, driving innovation in hardware design and validation.Core Expertise-Formal verification using symbolic computer algebra-Automated debugging and rectification of arithmetic/datapath circuits-Algorithm design for equivalence checking and circuit rectifiability-Graph-based verification leveraging AIGs and BDDs-SAT-based equivalence checking using miter models-FPGA prototyping and hardware acceleration frameworksGraphics IP validation across simulation, emulation, and FPGA platformsHighlights of My Work-Datapath Rectification: Developed a formal, computer-algebra-based approach for automated rectification of faulty datapath circuits at multiple nets. Implemented efficient algorithms for equivalence checking and function computation using Python and libraries like PolyBori, Singular, abc, and SIS-Synopsys R&D Internship: Researched state-of-the-art datapath verification techniques and enhanced the HECTOR Data Path Solver (HDPS). Built a robust, modular polynomial solver for verifying integer multipliers, improving flexibility over traditional pattern-based methods-FPGA Prototyping at Intel: Designed a transaction-based verification model for hardware acceleration of test benches. Delivered a framework combining emulation performance with simulation flexibility, adopted across teams and recognized with multiple awards-Graphics Validation at Intel: Led validation of complex graphics sub-IPs based on Microsoft DX11 specifications. Created frameworks to port post-silicon test cases across platforms (Simulation, Emulation, FPGA), improving efficiency and coverage.

Experience

1. Principal Engineer

   Synopsys Inc

   Feb 2025 — Present · Hillsboro, OR, US

Education

• University of Utah

  Doctor of Philosophy (Ph.D.), Computer Engineering

  2016

• Jssate

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2004 — 2008

• Manipal Institute of Technology

  Master's degree, VLSI

  2008 — 2010

Skills

• Vhdl
• Debugging
• Systemverilog
• Microprocessors
• Verilog
• Vlsi
• Modelsim
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• Soc
• Rtl Design
• Logic Design
• Functional Verification
• Perl
• Embedded Systems
• Tcl
• Asic