Vivekananda Dayananda

About Vivekananda Dayananda

An Electrical Engineering Graduate Student (VLSI and Architecture Design) at Arizona State University, Ira. A. Fulton School of Engineering.Core Competence in :•Computer Architecture, RTL Design, FSM, Synthesis and Design Verification.SVA, SVTB, functional coverage, Constrained Random test generation.FPGA Prototyping, AMBA AXI protocols, DDR, DMA, etc.•ASIC Design Flow: Floorplanning, Clock Tree Synthesis, APR, Timing Closure through ECO flows.•Standard Cell Library Design and Characterization in 32nm, 7nm Technology node.•Full-Custom Physical Design, Parasitic Extraction and Layout Verification (DRC,LVS). •Static Timing and Power Analysis. •Memory Design and Characterization in 7nm to 32nm Technology nodesSkills:• Software proficiency: Cadence (Layout, Virtuoso, Spectre, Encounter RTL Complier, ICFB, ELC), Modelsim, LTSpice, Synopsys(Hercules, SMC, StarRC, HSPICE, Primetime, CosmosScope, Wavewiewer),Mentor Graphics Calibre.Xilinx, Altera Quartus, Qsys. • HDL/HVL: Verilog.• Scripting Language: Unix Shell Scripting, PERL, TCL• Programming Languages: Embedded C, MIPS and x86 assembly language.• Operating Systems: Windows, Linux, unixI have substantial experience in custom Board design and product development at Bharat Electronics Limited. I have undergone a complete product development cycle.

Experience

1. Sr Applications Engineer

   Xilinx

   Sep 2018 — Present · US

   I have contributed to many of Xilinx reference designs (RDs) for Zynq US+ and VERSAL devices on Computer Vision and Networking. RDs featured multimedia pipelines with single/quad camera sensors for capture, Vitis accelerators or Codecs for processing, HDMI and audio systems for display. Other RDs featured deterministic real-time communication over Ethernet following 802.1 Qbv standards for time synchronization and traffic scheduling. In brief following are my contributions in various stages of project development.o Create Vivado Block design, Perform FPGA Synthesis, Place & Route, timing optimizations.o Created Custom RTL block for interfacing with AXI buso Developed a kernel driver for an ADC using IIO-framework handling events, triggered buffer and raw reads.o System bring up of complex SOC designs in Linux, system debug with Chipscope and design validation.o Create a Linux BSP which includes kernel drivers, custom device-tree and rootfs for the SOC.o Compile and link the Vitis Accelerator kernel with the platform logico Demonstrated user space application using Gstreamer framework with jupyter notebooks

Education

• Saint Josephs Central School

  High School

  2000 — 2007

• Arizona State University

  Master's degree, Integrated Circuit Design

  2016

• Visvesvaraya Technological University

  Bachelor's degree, Electrical and Electronics Engineering

  2007 — 2011

Skills

• Prime Time
• Cadence Virtuoso
• Linux
• C++
• Verilog
• Autocad
• Assembly Language
• Embedded C
• Matlab
• Cadence Encounter
• Very-Large-Scale Integration (Vlsi)
• Synopsis Hspice
• Perl
• Rtl
• C