Vivekanand Vivek

About Vivekanand Vivek

VLSI/ASIC Verification engineer having 7+ yrs. of experince in SoC Subsystem level verification and IP level verification using System Verilog and OVM/UVM as verification methodology. Successfully completed Functional Verification for various projects.Worked on different protocol as MIPI LLI, AMBA (APB, AXI), gDMA, PWM, I2C, UART, LPC, IOSF, Display, HDMI etc.Worked with different clients like Cisco, Microsoft, Mentor Graphics, Intel, Infinera, BEL & ADI.Experience in writing functional coverage and System Verilog Assertions.Worked on Creating Test Plan & Verification Plan, Developing Test bench from scratch, Writing test cases, Running regressions.

Experience

1. Senior Project Engineer

   Wipro

   Feb 2015 — Present

   Responsibility to develop the Test Plan and Verification Plan Document to create the Test bench with verification environment and verification component using System Verilog and UVM. To write and validate test cases and running regressions.

Education

• Bharath Institute of Higher Education and Research

  Engineer's Degree, Electrical and Electronics Engineering

  2005 — 2009

• R P M College

  +2 Higher Secondary School

• S. N. P. M. High School Madhepura

  Matriculation

Skills

• Functional Verification
• Systemverilog
• Uvm
• Open Verification Methodology
• Perl
• Verilog
• Vlsi