Vivek Surabhi

About Vivek Surabhi

FPGA Platform Architect & Design engineer with over 14 years of experience in industries spanning Autonomous Driving, Medical Robotics, Data Center Acceleration and IP Development - leading full development lifecycle through all phases from R&D prototypes to product deployment • Architecture of FPGA platforms for Autonomous Driving & Medical Robotics • Extensive experience with Video Processing, Video aggregation and multi sensor fusion & synchronization • Micro-architecture and RTL design of multi-clock domain, high speed digital logic, datapaths and connectivity IP\'s • PCIe, SERDES, DDR3/4, CAN, Camera(MIPI CSI-2),JESD, AXI4 Protocol and ARM Processors • Xilinx 7 Series, UltraScale, Zynq & MPSOC FPGA\'s and Vivado toolset with proficiency in floor-planning and timing closure • HW-SW integration, HW validation and prototyping on FPGA platforms • Hardware bring-up and board debug using scopes and analyzers • Verification and test bench creation with use of randomization, assertions, and coverage • Board design including schematic and layout overview, DFM and DVT Proven track record for successful completion and deployment of multiple systems and IP cores with emphasis and commitment to highest quality. Team contributor with proven mentoring and leadership abilities

Experience

1. Principal Member of Technical Staff

   AMD

   Sep 2023 — Present · San Jose, CA, US

Education

• Visvesvaraya Technological University

  Bachelor of Engineering, Electronics and Communication

  2002 — 2006

• Villanova University

  MS, Computer Engineering

  2006 — 2008

Skills

• Altera
• Digital Hardware Design
• Rtl Coding
• Power Analysis
• Board Layout
• Functional Verification
• Field-Programmable Gate Arrays (Fpga)
• Fpga
• Hardware Verification
• I2c
• Microprocessors
• Ncsim
• Board Bring-Up
• Modelsim
• Testing
• Clearcase
• Pcie
• Debugging
• Floorplanning
• Schematic Capture
• Spi
• Sr-Iov
• Ddr3
• Xilinx
• Rtl Design
• High Speed Design
• Scopes
• Logic Analyzer
• Vhdl
• Simulations
• Nc-Verilog
• Verilog
• Timing Closure
• C
• Tcl