Vivek Sakhare
Lead RTL Design Engineer-Professional II
- Role
- Lead Design Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vivek Sakhare
To Develop RTL, Timing Analysis, Design Analysis
Experience
Lead Design Engineer
May 2022 — Present · Bengaluru, IN
Development of RTL code using Verilog HDL or VHDL or System Verilog.Functional testing of Modules, Test cases review, User Constraint file creation.APB Protocol Synthesis, connectivity checks, Timing Analysis.
Education
Yeshwantrao Chavan College of Engineering - YCCE
Bachelor's degree, Electronics Engineering
2010 — 2014
Yeshwantrao Chavan College of Engineering - YCCE
Master's degree, VLSI Design
2014 — 2016
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