Vivek Periye

About Vivek Periye

15 Years experience in DFT domain• DFT architecture definition, implementation and validation starting from RTL-level using Synopsys TestMAX platform for Cores/Subsystem/SoC with Scan/MBIST/Boundary-Scan/SHS• Proficient in Verilog-based RTL coding and integration of DFT related logic • Scan Insertion, ATPG (DRC/Coverage Analysis/Diagnosis) and Scan patterns simulations• Hands-on experience in MBIST Implementation / MBIST Verification / Memory Repair / JTAG & Boundary Scan Implementation/Validation•Exposure to SoC and Block-level DFT timing constraints for BIST and Scan modes

Experience

1. Asic Implementation, Dft Engineer

   Meta

   Jan 2026 — Present · Bengaluru, IN

   Infrastructure Silicon

Education

• Amrita School Of Engineering

  Bachelor of Technology, Electronics and Communication Engineering

  2006 — 2010

Skills

• Xilinx Ise
• C
• Tcl
• Microcontrollers
• Ncsim
• Debugging
• Unix
• Clearcase
• Digital Circuit Design
• Vlsi
• Automatic Test Pattern Generation (Atpg)
• Vhdl
• Perl
• Embedded Systems
• C++
• Pbist
• Atpg
• Verilog
• Very-Large-Scale Integration (Vlsi)
• Rtl Design
• Tetramax
• Modelsim
• Dft
• Functional Verification
• Oop
• P1500
• Fpga
• Bist
• Jtag
• Memory Test
• Vcs