Vivek Gaurav
ASIC | RTL Design Engineer | System Verilog, Verilog | LINT, CDC, RDC | SpyGlass | Design Compiler | Timing Analysis
- Role
- Lead Engineer at Wipro
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Vivek Gaurav
Experienced Engineer with a demonstrated history of working in the information technology and services industry. Skilled in Verilog, Application-Specific Integrated Circuits (ASIC), Spyglass Lint and CDC. Hands on experience of LEC and FEV.
Experience
Lead Engineer
Nov 2021 — Present · Bengaluru, IN
RTL coding for ASIC IP Clock domain crossing LINT Design Compiler Formality Static Timimg Analysis
Education
Siksha 'O' Anusandhan University
Master of Technology - MTech, VLSI Design and Embedded System, 9.7/10
2015 — 2017
College of Engineering Bhubaneswar - India
Bachelor of Technology - BTech, Electronics and Telecommunication Engineering
2005 — 2009
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.