Vissu Burela
Silicon One @ Cisco
- Role
- Director Principal at Cisco
- Location
- Livermore, CA, US
- LinkedIn followers
- 500 followers
About Vissu Burela
Expert in ASIC Physical Design, Timing analysis and CAD flows.Specialties: All aspects of physical design including Place and Route, Timing, Extraction and EM/IR. Designing and setting up CAD flows and methodologies.
Experience
Director Principal
May 2024 — Present · San Jose, CA, US
STA / PD for networking chips powering next generation AI/cloud data centers
Education
Indian Institute of Science (IISc)
Master of Engineering (MEng), Systems Science and Automation
1994 — 1996
Stanford University
Strategic Decision and Risk Management, Business Administration and Management, General
2013 — 2014
Andhra University
BE, Electronics & Communication
1990 — 1994
Skills
- Tcl
- Integrated Circuit Design
- System on a Chip (Soc)
- Verilog
- Timing Closure
- Algorithms
- Physical Design
- Ic
- Perl
- Eda
- Application-Specific Integrated Circuits (Asic)
- Soc
- Semiconductors
- Asic
- Dft
- C
- Vlsi
- Virtuoso
- Place & Route
- Timing
- Semiconductor Industry
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