Vismay Kansara

About Vismay Kansara

I drive timing closure and signoff for high-performance SoCs — turning timing risk into delivery certainty.As an STA and Physical Design leader, I specialize in SoC-level timing convergence, quality signoff, and ECO-driven optimization for complex client and server chipsets. I’ve led multi-partition teams through full-chip signoff, balancing performance, power, and manufacturability across corners.My focus is on results — achieving clean signoff, ensuring robust timing, and mentoring engineers to deliver at scale. I bring a systematic approach to problem-solving and thrive in cross-functional environments, working closely with SD, DFx, clock, and physical design teams to drive timing closure end to end.Highlights• Published “Signoff Methodology for IPs/SS used as Hyperscale” – DTTC 2022• Recognized for quality-driven tape-ins and consistent on-time delivery• Delivered multiple generations of server SoCs with robust timing and clean signoff• Mentored engineers and interns, fostering technical growth and leadership skillsCore StrengthsSTA · Physical Design · SoC Integration · Timing Convergence · ECO Generation · Quality Signoff · Noise & DRV Closure · Cross-Functional Collaboration · Leadership & MentorshipIf you’re building SoC teams that demand precision, reliability, and results — let’s connect: v••••••••@gmail.com

Experience

1. Timing Engineer

   Broadcom

   Nov 2023 — Present · Bengaluru, IN

Education

• National Institute of Technology Surat

  Master of Technology - MTech, VLSI AND EMBEDDED SYSTEMS

• VVP Engineering College - India

  Bachelor of Engineering - BE, Electronics and Communications Engineering

Skills

• Matlab
• Vhdl
• C
• C++
• Embedded Systems
• Digital Image Processing
• Embedded C
• Programming
• Digital Electronics
• Windows
• Microsoft Excel
• Powerpoint
• Research
• Microsoft Word
• Electronics
• Javascript
• Microcontrollers
• Very-Large-Scale Integration (Vlsi)
• Verilog
• Rtl Design
• Eda
• System on a Chip (Soc)
• Field-Programmable Gate Arrays (Fpga)
• Application-Specific Integrated Circuits (Asic)
• Microsoft Powerpoint
• Linux
• Professional Mentoring
• Teamwork
• Teaching
• Simulations
• Microsoft Office
• Cadence Virtuoso
• Pspice
• Hardware Architecture
• Computer Architecture
• Xilinx Ise
• Cmos
• Systemverilog
• Spice
• Testing