Vishwas Vaidya

About Vishwas Vaidya

Over 20 years experience in ASIC front end design, micro architecture. Worked on multi-million gate designs on various technology nodes on complex ASICs. Worked on PCIe and CXL ArbMux, data link layer and logical phy layer for multiple generations.

Experience

1. Soc Design Engineer

   Intel

   Jun 2017 — Present · Bengaluru, IN

Skills

• Fpga
• Asic
• Rtl Coding
• Soc
• Mips
• Logic Design
• Tcl
• Debugging
• Eda
• Ic
• Rtl Design
• Altera
• Modelsim
• Vhdl
• X86
• Logic Synthesis
• Power Management
• Verilog
• Low-Power Design
• Integrated Circuit Design
• Systemverilog
• Static Timing Analysis
• Semiconductors
• Vlsi