Vishwas Raj

About Vishwas Raj

11+ years of experience in physical design. Of that 8+ is at intel.Have a good handle on Place and Route, Timing, Layout Cleanup and Verification-Skills and Tool Suite Experience-Tools : Fusion Compiler, ICC2, DC, Primetime, Innovus, Cadence Formality. Altair FT, Pandora-Scripting: Perl, Tcl, Python(basic)-

Experience

1. Staff Physical Design Engineer

   Intel

   Jul 2015 — Present · US

   Manager of a small team, that was involved in 2 project tapeouts.> Working as a IP Lead For Physical Design activity for a 30+ million gate count IP. Leading/Delegating tasks across different geographies. Was able to successfully deliver an on time, high quality delivery of the IP.> Work involved > Collaborating with different teams(across geos), to streamline our inputs/deliverables for physical design consumption.> Helped partition owners fix physical design challenges from placement, routing to Layout verification.> Overall IP Physical design implementation had multiple challenges, from many blocks pushing high utilization to channel partitions, which required scripting of placement logic to help ease timing and routing. Helped lead and close these tasks.> Also, helped lead the FEV part of this project.> 7+ million instance count Hierarchical APR implementation for MI design.> Earlier handled 2,3, 1+ million count Hierarchical APR, simultaneously.> Utilized a regression tool, for creating a setup for the entire team, to automate the whole Apr flow, increasing throughput and reducing Manual Errors. This was used to complete Apr for more than 9+ partitions. This increased the overall efficiency and quality of the team. I Wrote a technical paper on this, which was selected within the Company. I was also recognized for the efficiency improvement at department level.> Also Handling overall project flow technical support for Apr.

Education

• Arizona State University

  Master's degree, Electrical and Electronics Engineering

• JIIT( Jaypee Institute of Information Technology )

  Bachelor's Degree, ECE

  2005 — 2009

Skills

• Physical Design
• Cadence Virtuoso
• Vlsi
• Functional Verification
• Routing
• Floorplanning
• Integrated Circuit Design
• Microprocessors
• Timing Closure
• Static Timing Analysis
• Semiconductors
• Drc
• Formal Verification
• Floor Plans
• Asic
• Soc
• Clock Tree Synthesis
• Mixed Signal
• Tcl
• Analog
• Temporary Placement
• Systemverilog
• Analog Circuit Design
• Cadence