Vishwas Begur Venkatesh
- Role
- Asic Design Verification Engineer at Google
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vishwas Begur Venkatesh
I obtained my graduate degree in Electrical Engineering from the University of Minnesota,…
Experience
Asic Design Verification Engineer
Sep 2021 — Present
Skills
- Cosmosscope
- C++
- Microsoft Office
- System Verilog
- Teamwork
- Synopsys Tools
- Verilog
- Layout Versus Schematic (Lvs)
- Management
- Matlab
- Vhdl
- Design Rule Checking (Drc)
- C
- Cadence Virtuoso
- Xilinx Ise
- Java
- H-Spice
- Vcs
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