Vishnuvardhanaram Yara

Experience

1. Engineering Manager

   Intel

   May 2021 — Present · Bengaluru, IN

   Defining the memory controller and PHY design specs based on customer needs, providing architectures, micro architectures and delivering completely verified synthesizable high quality RTL for IPs with small team.Expertices in memory contollers and PHYs of DDR5/4/3, LPDDR5/4/3, QDR4,RLDRAM,HBM,APM,XSPI.Interconnect protocols like AXI4,CHI, APB,WB etc.Good knowledge is PCIE Driving the team on quality checks ( CDC, Lint, SDC quality ) for multiple IPs.Experienced in winning PD full chip projects and completely delivering high quality layout for tapeout.

Education

• Acharya Nagarjuna University (ANU), Guntur

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

  1996 — 2000

Skills

• Application-Specific Integrated Circuits (Asic)
• System on a Chip (Soc)
• Verilog
• Very-Large-Scale Integration (Vlsi)
• Asic
• Static Timing Analysis
• Rtl Design