Vishnu Uppula
Physical Design Specialist |Silicon Design Engineer |SOC | Low -Power-Designs | Advanced Node Technologies | Place and Route | ECO | PV | Sign-off
- Role
- Lead Design Engineer at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Vishnu Uppula
As a Lead Design Engineer at Cadence with over 7+ years of experience in physical design, I specialize in optimizing power, performance, and area metrics for advanced System-on-Chip (SoC) technologies. My work is dedicated to generating high-quality sign-off databases while addressing critical design challenges such as timing, congestion, and power optimization. Throughout my career, I have focused on delivering seamless RTL-to-GDS implementations and ensuring industry-leading silicon designs. By leveraging my expertise in MindMeister, power optimization, and advanced optimization techniques, I strive to contribute to innovative and efficient semiconductor solutions.
Experience
Lead Design Engineer
Jan 2025 — Present · Hyderabad, IN
Education
Kakatiya Institute of Technology & Science, Yerragattu Hillocks, Bheemaram, Hasanparthy, Warangal
Bachelor of Technology - BTech, Electrical and Electronics Engineering
2013 — 2017
CVR College of Engineering, Hyderabad
Master of Technology - MTech, VLSI SYSTEM DESIGN
2017 — 2019
Skills
- Engineering
- C
- Matlab
- C++
- Teamwork
- Windows
- English
- Autocad
- Microcontrollers
- Microsoft Office
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