Vishnu Shashidhara
Staff Engineer (Analog Mixed Signal ASIC Design Verification) @ Infineon Technologies | Verilog, System Verilog, UVM
- Role
- Staff Engineer (Design Verification) at Infineon Technologies
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Vishnu Shashidhara
Infineon Technologies benefits from a skilled Staff Engineer with over 7+ years of experience in analog and mixed-signal design verification for USB wired business unit products. The role focuses on leveraging SystemVerilog and UVM methodologies to ensure robust performance and compliance. Competency in Cadence tools and hardware simulators strengthens contributions to research and development initiatives. A research background at SDSU refined expertise in designing and verifying complex hardware systems like compressed sensing algorithms for neural signals, which was my Masters Thesis. Dedicated to delivering precise and innovative solutions, the work aligns with a mission to drive advancements in USB technology and efficient verification processes.
Experience
Staff Engineer (Design Verification)
Apr 2023 — Present · San Jose, CA, US
Working on USB wired BU Research and Development
Education
San Diego State University
Master’s Degree, Electrical and Electronics Engineering
2015 — 2017
Visvesvaraya Technological University
Bachelor’s Degree, Electrical, Electronics and Communications Engineering
2010 — 2014
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