Vishnu Kanchi

Engineering Manager, Analog and Mixed Signal Layout High Speed Serdes Ip @Synopsys Inc

Hyderabad, TG, IN
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Nov 2012 — Present

Engineering Manager, Analog and Mixed Signal Layout High Speed Serdes Ip @Synopsys Inc

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Responsible for the Analog and Custom Layout, Digital Verification Team working on high speed SERDES IP. Working on the CAD methodology improvements for the IP flowWorking with the P&R team on the Analog dot lib deliveryHiring and Resource Management

EDUCATION

1996 — 2000

Vasavi College of Engineering, Osmania University

Bachelor of Engineering, Electronics and Communications Engineering

2000 — 2002

Arizona State University

Master of Science, Electrical Engineering (Mixed Signal IC Design)

SKILLS

SpiceCadence VirtuosoEdaAsicDebuggingIcStatic Timing AnalysisVhdlPhysical VerificationVerilogIntegrated Circuit DesignDrcTclAnalogVlsiMixed SignalCircuit DesignSemiconductorsAnalog Circuit Design

ABOUT VISHNU KANCHI

Experience managing teams working on Analog and Mixed Signal LayoutsExperience in hiring top talent and responsible for hiring for SERDES IP team in AMS Design, Layout and Digital Verification. Experience working with global teams, tracking projects and ensuring teams meet schedule without compromising on qualitySolid understanding of DRC\'s, DFM and process issues at 40nm, 28nm and 20nm. Worked with the leading semiconductor companies and collaborated with them in developing the standard cell libraries using Cadabra for different process nodes in the leading fabs. Experience working with HSPICE, HSIM, Nanosim and possess good Knowledge of Synopsys Analog Mixed Signal Solutions Good knowledge of OpenAccess database and oaTclExperience in writing complex Pcells in TCL, Python. Involved in the PDK development for different process nodesGood Knowledge of transistor level circuit designStrong Communication and Writing SkillsAbility to multi-task, strong analytical and problem solving abilitySelf Starter and always have a ‘can do’ attitude while dealing with issues/problems. Willing to take up new challengesSpecialties: Standard Cell Library Design, PDK development, Thorough knowledge of Process rules and issues at 40nm, 28nm and 20nm, Analog IC design, Knowledge of the Analog design flow and the tools used - HSPICE, NANOSIM, HSIM, CSCOPE, WaveView, Custom Designer, Cadence Virtuoso, STAR -RC, Hercules, ICV, Calibre,Xcalibre

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Vishnu Kanchi — Engineering Manager, Analog and Mixed Signal Layout High Speed Serdes Ip at Synopsys Inc in Hyderabad, TG, IN | Unifers