Vishal Narkhede
Works @Google | ExQualcomm | ExANSYS | SoC | EMIR and ESD Signoff
- Role
- Full Chip Physical Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vishal Narkhede
o Experienced in all aspects of Power Integrity - IR/EM/ESD signoff, RDL and Floorplan design for PDN optimization.o Working as EMIR and ESD signoff lead for SoCs and critical sub-systems in SoC.o Key contribution for improving PDN signoff methodology and efficiency for faster and easy debug.o Cross Domain Learning: Worked for block level STA convergence and methodology.o Attributes include fast learner, team player and technically inclined.
Experience
Full Chip Physical Design Engineer
Aug 2023 — Present · Bengaluru, IN
Education
National Institute of Technology Karnataka
M.Tech, VLSI Design
2012 — 2014
Pimpri Chinchwad Education Trust'S. Pimpri Chinchwad College Of Engineering
B.E., Electronics and Tele-Communication
2008 — 2012
Skills
- Rtl Design
- Integrated Circuit Design
- Microprocessors
- Debugging
- C
- Embedded Systems
- Vlsi
- Vlsi Backend Design
- Verilog
- Very-Large-Scale Integration (Vlsi)
- Application-Specific Integrated Circuits (Asic)
- Static Timing Analysis
- Digital Ic Design
- Vhdl
- Field-Programmable Gate Arrays (Fpga)
- Soc
- Semiconductors
- Microcontrollers
- Asic
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