Vishal Manikwar
Staff Engineer - Asic Design Verification
- Role
- Mts Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Mts Silicon Design Engineer
Jan 2024 — Present · Hyderabad, IN
Education
Shri Guru Gobind Singh Institute of Engineering & Technology, Nanded, Maharashtra, India.
Bachelor’s Degree, Electronics and Telecommunication Engineering
2006 — 2010
National Institute of Technology, Tiruchirappalli
Master of Technology (M.Tech.)
2011 — 2013
Skills
- Digital Electronics
- Verilog Hdl
- Verilog
- Vlsi
- Digital Logic Design
- C
- Systemverilog
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.