Vishal Chauhan

About Vishal Chauhan

A Trained VLSI Design verification engineerSpecialties -→ ASIC/FPGA Design Flow→ Digital Design Methodologies→ SV / UVM based Verification Flow• Coding Languages-→ System Verilog → Verilog→ UVM→ C→ Python• Scripting -→Perl→ Makefile• Protocols -→ AMBA APB→ AMBA AHB→ AMBA AXI• Knowledge Of-→ Simulation→ Synthesis→ Verification→ Coverage\'s→ Assertions• EDA Tool -→ Xilinx : ISE and Vivado→ Mentor Graphics : ModelSim and QuestaSim→ Cadence : Incisive (NCSim) and Integrated Metrics Center (IMC)

Experience

1. Design Verification Engineer

   Incise Infotech Limited

   Nov 2021 — Present · Noida, IN

   In my role as a Design Verification Engineer at Incise Infotech Private Limited, I verified ODC projects like MIPI RFFE, I3C, DMA and SRAM, enhancing my SV and UVM knowledge. Collaborating with cross-functional teams, I ensured the successful verification of IP and SoC designs, contributing to the overall project success.

Education

• Shivalik Polytechnic

  Diploma of Education, Electronics and communication Engineering

• APJ Abdul Kalam Technological University

  Bachelor's degree, Electrical, Electronics and Communications Engineering