Virag Parekh

About Virag Parekh

Implementation Engineer with passion to build innovative products. Proven track record of delivering successful products and leading teams- Currently working in healthcare industry (stealth mode)- Led Physical design and implementation team, and worked with cross-functional teams to deliver multiple generations of successful Google\'s TPU (v3, v4, v5, v6)- First Arm64 bit Server and it\'s successors (Xgene-1, 2, 3 and Helix 1,2)- Worked on IBM\'s SERDES building Serdes and clock-diver circuits.Key skills include physical design and implementation, Top-level floorplaning, place and route, static timing analysis (STA), and logic equivalence checking (LEC), Verilog, TCL, Python with deep expertise in Cadence and Synopses tools.

Experience

1. Engineering Director and Principal Asic Architect

   Fortell

   Feb 2023 — Present · US

   We’re building technology that helps people reconnect with the world around them. Fortell’s AI-powered hearing aids make conversations clearer, not just louder. Join us.

Education

• University of Mumbai (Thadomal Shahani Engg College)

  Bachelor of Engineering, Electronics and Telecommunication

  2006 — 2009

• University of Southern California

  Masters of Science, Electrical Engineering

  2009 — 2011

Skills

• Rtl Coding
• Asic
• Verilog
• Floorplanning
• Vhdl
• Logic Synthesis
• Rtl Design
• Microprocessors
• System on a Chip (Soc)
• Hardware Architecture
• Logic Design
• Electrical Engineering
• Perl
• Eda
• Modelsim
• Circuit Design
• Tcl
• Static Timing Analysis
• Physical Design
• Debugging
• Spice
• Timing Closure
• Vlsi
• Cadence Virtuoso
• Systemverilog
• C++
• C
• Xilinx Ise
• Cadence
• Device Drivers
• Serdes