Vipul Sachdeva
Principal Engineer Synopsys | Ex Nsys | Ex Fibcom | MS RVCE ( ASIC Design) | B.Tech ( ECE )
- Role
- Principal Engineer at Synopsys Inc
- Location
- North Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Vipul Sachdeva
Skilled in Functional Verification, Verilog, System Verilog, VHDL, Field-Programmable Gate Arrays (FPGA), RTL coding and Logic Synthesis. Verification IP PCIE Gen1/2/3/4/5/6/7 Expertise.PIPE 7.0PIPE 6.0PIPE 5.1PIPE 4.4PIPE 4.3EthernetFunctional Coverage.Debugging Skills.Tools Expertise : VCS, Verdi, Model Sim, NCVTest planning, Test development, Verification Closure.
Experience
Principal Engineer
Mar 2025 — Present · Delhi, IN
Education
Guru Gobind Singh Indraprastha University
B.TECH, Electronics & Communication
2003 — 2007
RV College Of Engineering
MS, ASIC DESIGN
2008 — 2010
Skills
- Fpga
- Static Timing Analysis
- System Verilog
- Functional Verification
- Vlsi
- Logic Synthesis
- Open Verification Methodology
- Systemverilog
- Vhdl
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