Vipul Kumar
R&D Engineer at Synopsys
- Role
- R & d Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
R & d Engineer
Jul 2013 — Present
Working on high speed serdes design verification
Education
Kendriya Vidyalaya
Reva Institue of Technology (RITM)
Skills
- Sdio
- Fpga
- Asic
- Functional Verification
- Sd
- Verilog
- Open Verification Methodology
- Modelsim
- Ncsim
- C
- Systemverilog
- Axi4
- Perl , Systemverilog , Verilog , Shell Scripting
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