Vipul Jain
IC design engineer at Analog Devices || Indian Institute of Science, Bangalore
- Role
- Ic Design Engineer at Analog Devices
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
Experience
Ic Design Engineer
Jun 2019 — Present · Bengaluru, IN
1GHz Scable Low Voltage Signalling (SLVS) Transmitter in 28nm - Low Power IOsolution to GPS receiver.• Designed and analysed the SLVS driver for clock and Data transmissionwhich has VCM/Differential Swing conductibility.• Worked with Layout team & provided the suggestions for layout improvement. Kick Back Analysis of Delta Sigma ADC in Analog DFT bus in 16nm - Measure DCvoltages/currents of Analog sub-systems in IC.• Quantified the Kick back from ADc to the ADFT bus. 4GHz Clock routing in 16nm - A 4mm long routing of 8 clocks in parallel & 1synchronous clock.• Designed an innovative architecture to reduce power with very tighter dutycycle of 50 ± 2%.• Proposed on which metal layer clock routing should be done and what shouldbe the sizes of coaxial shields using EMX tool.• Worked with Layout team & provided the suggestions for layout improvement. Process Monitor in 16nm : Measures in which process the chip falls in.• Designed ring Oscillator of different flavours like ULVT,LVT,SVT,HVT,1p8Vdevices which has frequency quantification of different PVT corners.• Worked with Layout team & provided the suggestions for layout improvement. DIGIO in 16nm - It has TSMC CMOS GPIO (TX/RX)+ LVDS (TX/RX) in a single pad.• Analyzed the DIGIO performance & max frequency of IOs in different settings. 2GHz High Speed Control Interface (HSCI) in 16nm - Faster way to access thechip than the Standard SPI.• Analyzed the complete performance of the TX with different current settings.• Designed Delay Line with 100pS step size, used in EYE alignment algorithm. Analyzed the current noise to the gm-switch devices in 16nm. Reference Voltage generation with Constant output Resistance in 28nm• Designed an opamp and very low voltage current generation circuits.• Analyzed the loop gain and performances. 1GHz Sample and Hold circuit in 28nm.• Designed an opamp with 10GHz of UGF.• Designed a Bootstrap switch.
Education
Indian Institute of Science (IISc)
Master of Technology
2017 — 2019
Institute Of Engineering and Management
B.Tech
2013 — 2017
Shree Jain Vidyalaya
Higher Secondary
2011 — 2013
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