Vipul Agrawal
SDE2 @AMD | BITS Pilani
- Role
- Silicon Design Engineer 2 at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vipul Agrawal
IP Integration,LINT,PARBA,OA checks,IORING (Padring),Repeater, VCS, Verdi,RTL…
Experience
Silicon Design Engineer 2
Jul 2023 — Present · Hyderabad, IN
Education
Institute of Engineering and Technology
Bachelor of Technology in ECE
2015 — 2019
Birla Institute of Technology and Science, Pilani
Master of Engineering in Microelectronics
2021 — 2023
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