Viplove Rakheja

WORK HISTORY

EDUCATION

SKILLS

ABOUT VIPLOVE RAKHEJA

Staff AI Design Verification Engineer at Tenstorrent,graduated from NC State University as a Computer Engineer with specialization in ASIC Verification. Technical Skills:Languages: SystemVerilog, UVM, Python, C,C++, Verilog,CUDA, Java, HTML Tools: UVM Framework, DVE, GIT, SVN, Modelsim/Questasim, Synopsys Design Compiler, HSPICE, VIVA XL, Cadence Virtuoso, Courses Taken : Advanced Verificatiom (UVM)|ASIC and FPGA Design | ASIC Verification | Microprocessor Architecture| Advanced Microprocessor Architecture(Enhancing IPC of RISC-V Simulator)| Architecture of Parallel Computers | Advanced Computer Architecture (GP-GPU and FPGA (openCL))| Advanced Computer Design (Beaglebone)| VLSI System DesignVerification Skills : Verification using SystemVerilog and UVM, Randomization, Assertions, Functional and Code Coverage, UVM Framework, Constrained Stimulus Generation, Scoreboards, Predictor Models, Computer/ Microprocessor Architecture Skills : Cache and memory hierarchy, In-order Pipeline, Hazards, Branch Prediction, Out of order Superscalar processor, Tomasulo’s Algorithm, Cache Coherency, Load/store queue, Cache coherency protocols, modern superscalar microarchitecture, multithreading architecture, advanced speculation techniques, Chip Multi-Processor (CMP) architecture, Domain specific architecture, Non volatile memory and memory persistency, Processor securityDesign Skills : RTL Design, Logic Synthesis, Timing analysis, CMOS logic design, Parasitic Extraction, Logical effort, Dynamic logic design