Vipin Gopakumar Warrier

About Vipin Gopakumar Warrier

I have close to 15 years of experience in VLSI.I started my career with VLSI front end design for FPGAs. I had a good opportunity of going through the entire scheme of understanding top level system requirements to jotting down FPGA level requirements to coding and all the way down to binary file generation to be downloaded into FPGAs. I could work on some interesting designs in Networking and Aerospace domains.From FPGAs I moved onto ASIC. I could work on, ASIC implementation (Synthesis, EC and STA + a flavor of back-end(PD)) for couple of big multi-million gate chips. I got some quality hands-on and detailed insight into ASIC implementation.Currently, since last 10 years I am into ASIC design which is not limited to understanding requirements for new blocks, RTL coding, RTL integration at chip level, consultation for ASIC implementation and consultation to firmware & software teams. My immediate goal would be to take responsibility of a full chip tape out. Further on to a family of chips. Architect new generation chips. Set the road map for chip giants and manufacturers. and so on.

Experience

1. Principal Engineer

   Broadcom

   Sep 2012 — Present · Bangalore, IN

   RTL Design & implementation

Education

• NSS College of Engineering

  B-Tech

  1998 — 2002

• Amrita Institute of Technology

  M-Tech

  2003 — 2005

Skills

• Debugging
• Systemverilog
• Tcl
• Ic
• Modelsim
• Vlsi
• Vhdl
• Verilog
• Perl
• Rtl Design
• Rtl Coding
• Static Timing Analysis
• Arm
• Functional Verification
• Soc
• Fpga
• Asic
• Logic Synthesis