Vinoth Elumalai

About Vinoth Elumalai

Around 12+ years of experience in FPGA and ASIC RTL Design and Synthesis- Experience in writing design specification, Micro-Architecture design, VHDL & Verilog RTL logic coding, logic synthesis and verification- Experience with Low Power design, Synthesis, Timing Constrains, STA, DSP Slices,(PSL) Assertions, Glue Logic,and Simulation based Verification- Experience in ASIC design flows including PLDRC Linting, CDC checks, Synthesis, formal verification (LEC) and related tools- Lead the verification effort for generating test benches using Vhdl and Verilog-hdl- Experience in SOC Integration level activities- Experience in Synthesis with optimization, Design Constraints, Placement & Routing, and Implementation- Familiar with design, development and integration of design blocks (IP) for system-on-chip (SoC) components.

Experience

1. Senior Staff Engineer

   Qualcomm

   Sep 2019 — Present · Bengaluru, IN

Education

• Anna University Chennai

  Bachelor of Engineering, Electronics and Communication

  2005 — 2009

Skills

• C
• Microcontrollers
• R&D
• Rtl Design
• Pcb Design
• Simulation
• Labview
• Logic Synthesis
• Signal Processing
• Matlab
• Electronics
• Arm
• Rtl Coding
• Rf
• Xilinx
• Engineering
• Dsp
• C++
• Algorithms
• Vlsi
• Semiconductors
• Functional Verification
• Orcad
• Field-Programmable Gate Arrays (Fpga)
• Modelsim
• Tcl
• Testing
• Verilog
• Vhdl
• Simulations
• Digital Signal Processors
• Fpga
• Embedded Software
• Asic
• Perl
• Embedded Systems